Tata Institute of Fundamental Research
Dual Capacity Upper Bounds for Runlength Constrained Channels
STCS Colloquium
Speaker:
Andrew Thangaraj (Indian Institute of Technology
Department of Electrical Engineering
Chennai 600036)
Organiser:
Rahul Vaze
Date:
Tuesday, 29 Nov 2016, 16:00 to 17:00
Venue:
A-201 (STCS Seminar Room)
(Scan to add to calendar)
Abstract:
Characterising the capacity of channels with memory is a challenging and interesting problem in information theory. One example is a channel with an input runlength constraint. The runlength constraint is popular in data storage applications and limits the minimum and maximum number of 0s between consecutive 1s in the input sequence. The noiseless capacity or enumeration of runlength constrained sequences was presented by Shannon in his 1948 paper. However, for a noisy channel with an input runlength constraint, the capacity has been difficult to characterise with attempts by several researchers over the last 35 years or so. In this talk, we will describe the dual method for obtaining upper bounds on capacity and discuss its application to noisy runlength-constrained channels. We will show that the dual upper bound for noisy runlength-constrained channels reduces to simple (and sometimes elegant) algebraic expressions for discrete channels, and is very close to achievable rates for several channels of theoretical and practical importance. We will conclude by briefly discussing other applications of the dual bound including peak-power limited Gaussian channels and ISI channels.
Bio: Andrew Thangaraj received his B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT), Madras, India in 1998 and a PhD in Electrical Engineering from the Georgia Institute of Technology, Atlanta, USA in 2003. He was a post-doctoral researcher at the GTL-CNRS Telecom lab at Georgia Tech Lorraine, Metz, France from August 2003 to May 2004. From June 2004, he has been with the Department of Electrical Engineering, IIT Madras, where he is currently a professor. Since Jan 2012, he has been serving as Editor for the IEEE Transactions on Communications. His research interests are in coding theory, information theory and information-theoretic aspects of cryptography.
Since Oct 2011, he has been serving as NPTEL coordinator at IIT Madras. He has played a key role in initiating and running NPTEL online courses and certification. He is currently a National MOOCs Coordinator for NPTEL in the SWAYAM project of the MHRD.
| Speaker: | Andrew Thangaraj (Indian Institute of Technology Department of Electrical Engineering Chennai 600036) |
| Organiser: | Rahul Vaze |
| Date: | Tuesday, 29 Nov 2016, 16:00 to 17:00 |
| Venue: | A-201 (STCS Seminar Room) |
(Scan to add to calendar)
Abstract:
Characterising the capacity of channels with memory is a challenging and interesting problem in information theory. One example is a channel with an input runlength constraint. The runlength constraint is popular in data storage applications and limits the minimum and maximum number of 0s between consecutive 1s in the input sequence. The noiseless capacity or enumeration of runlength constrained sequences was presented by Shannon in his 1948 paper. However, for a noisy channel with an input runlength constraint, the capacity has been difficult to characterise with attempts by several researchers over the last 35 years or so. In this talk, we will describe the dual method for obtaining upper bounds on capacity and discuss its application to noisy runlength-constrained channels. We will show that the dual upper bound for noisy runlength-constrained channels reduces to simple (and sometimes elegant) algebraic expressions for discrete channels, and is very close to achievable rates for several channels of theoretical and practical importance. We will conclude by briefly discussing other applications of the dual bound including peak-power limited Gaussian channels and ISI channels.
Bio: Andrew Thangaraj received his B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT), Madras, India in 1998 and a PhD in Electrical Engineering from the Georgia Institute of Technology, Atlanta, USA in 2003. He was a post-doctoral researcher at the GTL-CNRS Telecom lab at Georgia Tech Lorraine, Metz, France from August 2003 to May 2004. From June 2004, he has been with the Department of Electrical Engineering, IIT Madras, where he is currently a professor. Since Jan 2012, he has been serving as Editor for the IEEE Transactions on Communications. His research interests are in coding theory, information theory and information-theoretic aspects of cryptography.
Since Oct 2011, he has been serving as NPTEL coordinator at IIT Madras. He has played a key role in initiating and running NPTEL online courses and certification. He is currently a National MOOCs Coordinator for NPTEL in the SWAYAM project of the MHRD.
Bio: Andrew Thangaraj received his B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT), Madras, India in 1998 and a PhD in Electrical Engineering from the Georgia Institute of Technology, Atlanta, USA in 2003. He was a post-doctoral researcher at the GTL-CNRS Telecom lab at Georgia Tech Lorraine, Metz, France from August 2003 to May 2004. From June 2004, he has been with the Department of Electrical Engineering, IIT Madras, where he is currently a professor. Since Jan 2012, he has been serving as Editor for the IEEE Transactions on Communications. His research interests are in coding theory, information theory and information-theoretic aspects of cryptography.
Since Oct 2011, he has been serving as NPTEL coordinator at IIT Madras. He has played a key role in initiating and running NPTEL online courses and certification. He is currently a National MOOCs Coordinator for NPTEL in the SWAYAM project of the MHRD.