Software Verification: Trends and Challenges

Speaker:
R. Venkatesh
Date:
Friday, 9 Dec 2016, 16:00 to 17:00
Venue:
AG-66 (Lecture Theatre)
Category:
Abstract
The influence of software in our daily lives is only increasing, especially its role in automating critical tasks like surgery and self driving. It is therefore imperative that we have some techniques to assure that the software that we rely on does will not take decisions that will harm humans and be potentially fatal. Yet, the advances in verification continues to lag the advances in automation. In this talk we will introduce the various approaches that have been taken by the verification community to show that software will be safe, present the challenges faced by the community and look at where we stand today.

Bio: R. Venkatesh is a chief scientist with TCS Research and heads its Verification and Validation Program. He has been with TCS for more than 25 years primarily in the areas of software development, formal methods and verification. During this tenure he has lead several tool development projects including TCS ECA a static analysis tool that is sold commercially by TCS. Other tools include MasterCraft and more recently a formal specification notation EDT.